G. MOORE, "Cramming More Components onto Integrated Circuits", Electronics,
p114-117, April 1965. (Also in "Readings in Computer Architecture," pages 56-59 + Editor intro pages 13-14.)

J. S. LIPTAY, "Structural Aspects of the System/360 Model 85, Part II: The Cache", IBM
Systems Journal,, 7, 1 (1968), 15-21). (Also in "Readings in Computer Architecture," pages 373-379 + Editor intro pages 364-65.)

 J.GRAY, Turing Award Lecture: "What Next? A dozen remaining IT problems"(1999)

 Hennessy, J. "The future of systems research." Computer, vol.32, (no.8), IEEE Comput. Soc, Aug. 1999.

 G. M. AMDAHL, "Validity of the Single-Processor Approach to Achieving Large Scale
Computing Capabilities", AFIPS Conference Proceedings, (April 1967), 483-485.
(Also in "Readings in Computer Architecture," pages 79-81 + Editor intro pages 70-71.)

 Gibson, J.; Kunz, R.; Ofelt, D.; Horowitz, M.; Hennessy, J.; Heinrich, M. "FLASH vs. (simulated) FLASH: closing the simulation loop." Operating Systems Review, vol.34, (no.5), (ASPLOS-IX. Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, USA, 12-15 Nov. 2000.) ACM, Dec. 2000. Also see about Flash in ISCA Retrospective.

 R. M. RUSSELL, "The Cray-1 Computer System", Comm. ACM, 21, 1 (January 1978),
63-72. (Also in "Readings in Computer Architecture," pages 40-49 + Editor intro pages 8-9.)

M. J. FLYNN, " Very High-Speed Computing Systems", Proceedings of the IEEE , vol.
54, no. 12, December 1966. (Also in "Readings in Computer Architecture," pages 519-527 + Editor intro pages 515-517.

Anant Agarwal et all, "The MIT Alewife Machine: Architecture and Performance" (.ps.Z) , December 1994.

SoftFLASH: Analyzing the Performance of Clustered Distributed Virtual Shared Memory
Andrew Erlichson: Stanford University, Neal Nuckolls, Greg Chesson: Silicon Graphics, Inc. and John Hennessy: Stanford University.

Jouppi, N. P.; Wall, D. W., "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines,".

Lebeck, A., Wood, D., "Cache Profiling and the SPEC Benchmarks: A Case Study,"

Wu, P., Huang, K., "Case Studies on Cache Performance and Optimization of Programs with Unit Strides,"

Reading for Case Studies

• Pentium-Pro
  • Shen and Lipasti: Chapter 7 "Intel's P6 Microarchitecture", Colwell et al.
  • Tuning the Pentium Pro Microarchitecture, Papworth (Don't bother trying to read the grey section on the third page (pg. 10) since the poor scanning makes it pretty much illegible.)
• Alpha 21264
  • The Alpha 21264 Microprocessor, Kessler
  • Circuit Implementation of a 600MHz Superscalar RISC Microprocessor, Matson et al.
  • We briefly mentioned CAM-based renamers. See Section 2.1 of the paper Physical Register Inlining (Lipasti et al.) for a good explanation of how this works.
• Pentium 4
  • The Microarchitecture of the Pentium 4 Processor, Hinton et al.
  • A 0.18um CMOS IA-32 Processor with a 4-GHz Integer Execution Unit, Hinton et al.
  • The Intel Pentium 4 Processor, Carmean (talk slides); if you're interested in seeing the original talk, follow this link
• AMD K7/K8
  • The AMD Athlon XP Processor with 512KB L2 Cache, Huynh (white paper)
  • The AMD Opteron Processor for Multiprocessor Servers, Keltcher et al.
  • AMD's Next Generation Microprocessor Architecture, Weber (MPF talk slides)
  • AMD's Hammer micro architecture preview, de Vries (Opteron reverse engineering based on analysis of patents)
  • The AMD Opteron Processor For Mutliprocessor Servers, IEEE Micro, IEEE Computer Society, March-April 2003, pp 66-76
    
• Pentium-M
  • The Intel Pentium M Processor: Microarchitecture and Performance, Gochman et al.
  • Let's speculate and try to decipher the details of the next-generation Pentium-M:
    • Fall IDF 2005 - Day 1: Intel's New Architecture Details Revealed, Lai Shimpi
    • Fall IDF 2005: Intel's unified processor architecture, Hannibal
    • Intel reveals details of new CPU design, Wasson
• Itanium 2 and Montecito
  • Itanium 2 Processor Microarchitecture, McNairy et al.
  • Montecito: A Dual-Core, Dual-Thread Itanium Processor, McNairy et al.
• Power4, Power5
  • Power4 System Design for High Reliability, Bossen et al.
  • IBM Power5 Chip: A Dual-Core Multithreaded Processor, Kalla et al.
• UltraSPARC, Niagara
  • UltraSPARC-III: Designing Third-Generation 64-Bit Performance, Horel et al.
  • Niagara: A 32-Way Multithreaded SPARC Processor, Kongetira et al.

• IBM/Sony Cell
  • Power Efficient Processor Architecture and The Cell Processor, Hogstee
  • Power-Conscious Design of the Cell Processor's Synergistic Processor Element, Takahashi et al.
• GPU/NVIDIA
• CudaPerformance:
  

•  Fermi Architecture (White paper)

• NVIDIA TESLA: A Unified Graphics and Computing Architecture, Erik Lindholm, John Nickolls, Stuart Oberman, John Montrym, IEEE MicroMarch-April 2008, pp. 39-55.
  

Web Links

• WWW Computer Architecture Page: Listing of conferences, people, other comp arch information.
• USENET comp.arch: Internet newsgroup, unfortunately the signal-to-noise ratio has dropped over recent years.
• Real World Technologies: A more technical forum with IMO higher quality discussions than comp.arch, but the posting activity is lower. Also has some interesting articles.
• Tom's Hardware: More consumer and enthusiast oriented, but has some interesting high-level descriptions of processor architectures and all of the latest benchmark results.
• At Random: Monthly column in the IEEE Computer Society magazine from Bob Colwell (chief architect of multiple Pentiums). Not all articles are about processors, but they're almost always entertaining to read.
• Intel Microprocessor Hall of Fame: Stroll down memory-lane starting from the original 4004. Die photos for most older CPUs. Only goes up to the first P4.
• Investigations into the Sparc Architecture: Provides a structured description of Sparc architectural design in detail.